In addition to the necessary properties, including a relatively small size and a low electric leakage level, components for hand-held, battery-powered electronic devices are also required to have a property of rapid switching speed. A P-type LDMOS device generally includes an array of multiple gates, which enables an output current of greater than 10 A, and is hence widely used in power management circuits of hand-held electronic products. As a large gate array leads to a great total gate width, how to achieve a high uniformity to ensure a low electric leakage level is a crucial issue for P-type LDMOS devices. On the other hand, there is a contradiction that, although a high switching speed requires a low threshold voltage, the latter typically causes a relatively high leakage current. Compared with buried-channel devices, surface-channel devices can be compromised between a low threshold voltage and a low electric leakage level. FIG. 1 shows a conventional P-type LDMOS device, which includes an N-type substrate 1′, an N-type epitaxial region 2′, an N-type channel 5′, a first lightly doped drain drift diffusion region 6′, a second lightly doped drain drift diffusion region 7′, a heavily doped N-type polysilicon sinker 3′, a gate oxide layer 9′, a polysilicon gate 4′, a tungsten/silicon bi-layer 8′, a drain 10′, a source 11′, and polysilicon sidewall spacers 13′. Conventional methods for making the device include the skeleton steps of: growing an N-type epitaxial layer 2′ over the heavily doped N-type substrate 1′; etching the N-type epitaxial layer 2′ to form a deep trench therein, filling heavily doped N-type polysilicon in the deep trench and etching the polysilicon back to the same level with a top surface of the epitaxial layer 2′, thereby forming the heavily doped N-type polysilicon sinker 3′; performing a first P-type ion implantation to form the first lightly doped drain drift diffusion region 6′; growing the gate oxide layer 9′, depositing thereon P-type doped polysilicon and a tungsten/silicon bi-layer, and performing photolithography and dry etching processes thereon to form a gate structure comprised of the polysilicon gate 4′ and the tungsten/silicon bi-layer 8′; performing an N-type channel ion implantation process and a rapid thermal annealing process to form the N-type channel 5′; performing a second P-type ion implantation to form the second lightly doped drain drift diffusion region 7′; depositing a dielectric layer and etching it to form the polysilicon sidewall spacers 13′; forming the source and drain by photolithography and ion implantation processes, followed by a rapid thermal annealing process for activating the whole structure; and completing the device after forming metal silicide pads 12′, contact holes and metal connections (not shown).
In such methods, in order to prevent the P-type impurity (which is typically boron) contained in the polysilicon gate 4′ from penetrating through the gate oxide layer 9′ and entering the tungsten/silicon bi-layer 8′, a rapid thermal annealing process is adopted to form the N-type channel 5′. This may easily lead to a relatively short channel with a greatly inter-process variation in its length. Although it is applicable to substitute the rapid thermal annealing process for a long-time high-temperature drive-in process to avoid the short channel effect, the latter may cause impurity in the heavily doped polysilicon deposited in the deep trench to diffuse into the channel 5′ and boron in the gate structure to easily penetrate through the gate oxide layer 9′ and enter the channel 5′. Moreover, as the tungsten/silicon bi-layer has a higher dissolving capability to solid boron than polysilicon, forming the gate structure with the polysilicon gate 4′ and the tungsten/silicon bi-layer 8′ may lead to the diffusion of boron into the tungsten/silicon bi-layer 8′, thus decreasing the boron content of the polysilicon gate 4′ and increasing the proneness of the device to be depleted. All the above problems may increase the non-uniformity of threshold voltage and other properties of the device.